Computing devices are prevalent in society. These devices may include servers, computers, cellular telephones, portable digital assistants (“PDAs”), portable game consoles, palmtop computers, and other electronic devices. Computing devices conventionally include a processor-based system that performs computational tasks in a wide variety of applications. The processor-based system may be included with other integrated circuits designed to work together in a system-on-a-chip (“SoC”), to deliver functionality to a user. A typical processor-based system includes one or more processors that execute software instructions. For example, some software instructions instruct a processor to fetch data from a location in a memory, perform one or more processor operations using the fetched data, and generate a stored result. As examples, software instructions can be stored in a system or some type of memory such as a main memory. The software instructions can also be stored in a specific type of memory such as a cache memory that allows faster access. For example, the cache memory (“cache”) can be a cache memory local to the processor, a shared local cache among processors in a processor block, a shared cache among multiple processor blocks, or a main memory of the processor-based system. As processor-based systems increase in complexity and performance, the memory capacity requirements of memory may also increase. However, providing additional memory capacity in a processor-based system increases cost and area needed for memory on an integrated circuit.
As an alternative, data compression is a promising approach for meeting the increasing memory capacity demands expected in future systems. Unfortunately, existing compression algorithms do not translate well when directly applied to main memory because they require the memory controller to perform non-trivial computations to locate a cache line within a compressed memory page, thereby increasing access latency and degrading system performance. As a result, for example, accessing a particular cache line in memory may require access to metadata in the memory and an additional layer of address computation to determine the location of the compressed cache line in memory corresponding to the particular cache line. This can increase complexity, cost, and latency to a processor-based system employing memory capacity compression.
Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional approaches including the methods, system and apparatus provided hereby.